With reference to FIG. 1, master-slave type delay locked loops (DLLs) generally use two primary components, a master DLL 102 and at least 1 slave DLL 108. The Master DLL locks to a certain delay for a given reference clock (Ref Clk) and communicates the delay information to the slave DLL 108 via a Control Bias voltage signal generated by a replica bias generator circuit 104. The slave DLL then generates an output signal (Output) based on an applied input (Input) signal delayed by an amount corresponding to the Control Bias signal. Copies of the bias signal, which carry the Master DLL's delay information, may be sent to various other slave DLLs to control their delay characteristics to mimic those of the master.
Master and slave DLLs can be configured in a variety of different ways. For example, a master DLL (such as master DLL 102) may comprise a phase-frequency detector, a charge pump, a loop filter, and a programmable voltage controlled delay line (VCDL), coupled as is commonly known, to generate a clock with desired delay characteristics from an applied reference clock (Ref Clk) and a self-generated feedback clock (Feedback Clk). Likewise, a suitable slave DLL to work in cooperation with the master DLL may include its own VCDL, along with a phase interpolator for added granularity.
The replica bias generator circuit 104 generates a replica of a bias signal (internal to the master DLL) used to control the master DLL circuit's VCDL. This replica bias signal (Control Bias) is provided to the slave VCDL (by way of a pass transistor M1 and wake up circuit 110 as a Slave Bias signal) to control the delay of the signal applied to the slave DLL 108 in accordance with the desired delay that is generated at the master DLL circuit 102. (Note that the bias generator or replica bias generator may actually be part of the master DLL, providing the bias signal to both the master and slave DLLs, or alternatively, as is shown in FIG. 1, it may be a separate circuit to replicate, or create a suitable derivation of, a bias signal generated from the master DLL circuit.
A slave DLL is considered to be on and consume power when it is biased, i.e., when a voltage is applied at its Slave Bias input. Usually, the slaves contain a large amount of capacitance on their bias inputs due to the loading gate capacitance and extra capacitors that are commonly added for noise immunity. This large capacitance can cause the slave to require a substantial amount of time (e.g., on the order of 100 ns) to charge up and settle for normal operation. In many applications, this large time factor limits how often the slaves could be powered down and thus inhibits putting them into a low power state in order to reduce power consumption. For example, with double data rate (DDR) memory interface applications, slave DLLs are used to delay the DQS (data strobe) signal from the memory to widen the read eye during read mode. The time between initiating a READ and when the strobe signal from the memory reaches the slave circuit is on the order of 10-20 nS. Thus, the 100 nS time required to power up a slave is too long for it to be in a power down mode and then be awoken when a read operation is initiated.
Accordingly, wake-up circuits such as wake-up circuit 110 are employed to more quickly charge up the slave circuit 108 so that it can be powered down and re-started in a sufficiently small amount of time. Wake-up circuit 110 comprises comparator U1 and pull-up transistor M2 coupled to the master and slave circuits as shown. In operation, during a powered down mode (master DLL 102 remains on), the Active Slave signal is de-asserted so that M1 is off, and the Wake-up signal is also de-asserted to disable U1. U1 is configured to output a High value when it is disabled. Thus, during the powered down mode, the Control Bias signal is decoupled from the Slave Bias input, which charges down.
When the slave circuit 108 is to be activated, the Wake-up signal is asserted to activate comparator U1. The Control Bias signal will be higher than the Slave Bias signal, so comparator U1 outputs a low and turns on pull-up transistor M2. This causes the Slave Bias node to charge up more quickly than it would if it were simply coupled to the Control Bias signal through pass gate M1. The comparator keeps the pull-up transistor M2 on until the Slave Bias level reaches the level of the Control Bias signal, whereupon U1 outputs a high level and turns off M2. The controller 106 is configured so that the Active slave signal asserts and the Wake-up signal de-asserts at a set time to coincide with this occurrence.